[dm-crypt] [dm-devel] dm-crypt performance

Arno Wagner arno at wagner.name
Mon Apr 22 04:28:04 CEST 2013

On Sun, Apr 21, 2013 at 10:38:36PM +0200, Yves-Alexis Perez wrote:
> On mar., 2013-04-09 at 20:40 +0200, Arno Wagner wrote:
> > > AES uses data-dependent lookup tables, on CPU with hyperthreding, the 
> > > second thread can observe L1 cache footprint done by the first thread and 
> > > get some information about data being encrypted...
> > 
> > Yes, but that is not the only potential problem. For example, with 
> > Intel now implementing voltage regulators on the CPU, we may
> > even see power-usage based leaks. If you are paranoid, constant
> > time-contant-power implementations are the only solution. And 
> > while feasible, they are sloooooooowwwwww... 
> Note that on those CPUs AES should usually use AES-NI so timing attacks
> using the cache should not be that relevant…

I should point out that I talk about "power" and not "time".

Arno Wagner,     Dr. sc. techn., Dipl. Inform.,    Email: arno at wagner.name
GnuPG: ID: CB5D9718  FP: 12D6 C03B 1B30 33BB 13CF  B774 E35C 5FA1 CB5D 9718
There are two ways of constructing a software design: One way is to make it
so simple that there are obviously no deficiencies, and the other way is to
make it so complicated that there are no obvious deficiencies. The first
method is far more difficult.  --Tony Hoare

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